SC9RS08KA2 datasheet(40/134 Pages) FREESCALE

40 / 134 page

Chapter 5 Resets, Interrupts, and General System Control

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

5.8.3

System Device Identification Register (SDIDH, SDIDL)

These high page read-only registers are included so host development systems can identify the RS08

derivative and revision number. This allows the development software to recognize where specific

memory blocks, registers, and control bits are located in a target MCU.

1. The revision number that is hard coded into these bits reflects the current silicon revision level.

Figure 5-3. System Device Identification Register — High (SDIDH)

Table 5-3. SOPT Register Field Descriptions

Field

Description

COPE

COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.

0 COP watchdog timer disabled.

1 COP watchdog timer enabled (force reset on timeout).

COPT

COP Watchdog Timeout — This write-once bit selects the timeout period of the COP.

0 Short timeout period selected.

1 Long timeout period selected.

STOPE

Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user

program attempts to execute a STOP instruction, an illegal opcode reset is forced.

0 Stop mode disabled.

1 Stop mode enabled.

BKGDPE1,2

1 When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is

disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active

BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.

2 BKGDPE can only write once from value 1 to 0. Writing from value 0 to 1 by user software is not allowed. BKGDPE can be

changed back to 1 only by a POR or reset with proper condition as stated in Note 1.

Background Debug Mode Pin Enable — This write-once bit when set enables the PTA3/ACMPO/BKGD/MS

pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This

pin defaults to the BKGD/MS function following any MCU reset.

0 PTA3/ACMPO/BKGD/MS pin functions as PTA3 or ACMPO.

1 PTA3/ACMPO/BKGD/MS pin functions as BKGD/MS.

RSTPE

RESET Pin Enable — When set, this write-once bit enables the PTA2/KBIP2/TCLK/RESET/VPP pin to function

as RESET. When clear, the pin functions as one of its input-only alternative functions. This pin is input-only port

function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.

0 PTA2/KBIP2/TCLK/RESET/VPP pin functions as PTA2/KBIP2/TCLK/VPP.

1 PTA2/KBIP2/TCLK/RESET/VPP pin functions as RESET/VPP.

321

REV3

REV2

REV1

REV0

ID11

ID10

ID9

ID8

Reset:

0 (Note 1)

= Unimplemented or Reserved

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