SC9RS08KA2 datasheet(39/134 Pages) FREESCALE

39 / 134 page

Chapter 5 Resets, Interrupts, and General System Control

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

5.8.2

System Options Register (SOPT)

This high page register is a write-once register so only the first write after reset is honored. It can be read

at any time. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid

accidental changes to these sensitive settings. SOPT must be written during the user’s reset initialization

program to set the desired controls even if the desired settings are the same as the reset settings.

1. When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is

disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active

BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.

Table 5-2. SRS Field Descriptions

Field

Description

POR

Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was

ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while

the internal supply was below the LVR threshold.

0 Reset not caused by POR.

1 POR caused reset.

External Reset Pin — Reset was caused by an active-low level on the external reset pin.

0 Reset not caused by external reset pin.

1 External reset pin caused reset.

COP

Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.

This reset source can be blocked by COPE = 0.

0 Reset not caused by COP timeout.

1 COP timeout caused reset.

ILOP

Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP

instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is

considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.

0 Reset not caused by an illegal opcode.

1 An illegal opcode caused reset.

ILAD

Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented

memory address.

0 Reset not caused by an illegal address.

1 An illegal address caused reset.

LVD

Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will

occur. This bit is also set by POR.

0 Reset not caused by LVD trip or POR.

1 Either LVD trip or POR caused reset.

321

COPE

COPT

STOPE

BKGDPE

RSTPE

Reset:

1 (Note 1)

POR:

110

1 (Note1)

= Unimplemented or Reserved

u = Unaffected

Figure 5-2. System Options Register 1 (SOPT)

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