SC9RS08KA2 datasheet(36/134 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

•

Computer operating properly (COP) timer

•

Illegal opcode detect (ILOP)

•

Illegal address detect (ILAD)

•

Background debug forced reset via BDC command BDC_RESET

Each of these sources, with the exception of the background debug forced reset, has an associated bit in

the system reset status register (SRS).

5.4

Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset if the application software fails to execute as

expected. To prevent a system reset from the COP timer (when it is enabled), application software must

reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter

before it times out, a system reset is generated to force the system back to a known starting point.

After any reset, the COPE becomes set in SOPT, which enables the COP watchdog (see Section 5.8.2,

“System Options Register (SOPT),” for additional information). If the COP watchdog is not used in an

application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the

address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this

address is decoded and sends a reset signal to the COP counter.

There is an associated short and long time-out controlled by COPT in SOPT. Table 5-1 summaries the

control functions of the COPT bit. The COP watchdog operates from the 1-kHz clock source and defaults

to the associated long time-out (28 cycles).

Even if the application will use the reset default settings of COPE and COPT, the user should write to the

write-once SOPT registers during reset initialization to lock in the settings. That way, they cannot be

changed accidentally if the application program gets lost. The initial write to SOPT will reset the COP

counter.

In background debug mode, the COP counter will not increment.

When the MCU enters stop mode, the COP counter is re-initialized to zero upon entry to stop mode. The

COP counter begins from zero as soon as the MCU exits stop mode.

5.5

Interrupts

The SC9RS08KA2 Series does not include an interrupt controller with vector table lookup mechanism as

used on the HC08 and HCS08 devices. However, the interrupt sources from modules such as LVD, KBI,

Table 5-1. COP Configuration Options

COPT

COP Overflow Count1

1 Values shown in this column are based on

tRTI ≈ 1 ms. See tRTI in the Section A.9.1, “Control

Timing,” for the tolerance of this value.

025 cycles (32 ms)

128 cycles (256 ms)

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