SC9RS08KA2 datasheet(78/134 Pages) FREESCALE

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Internal Clock Source (RS08ICSV1)

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

9.3.2

ICS Control Register 2 (ICSC2)

432

CLKS

IREFSTEN

Reset:

= Unimplemented

Figure 9-3. ICS Control Register 1 (ICSC1)

Table 9-2. ICSC1 Field Descriptions

Field

Description

CLKS

Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency

depends on the value of the BDIV bits.

0 Output of FLL is selected

1 Internal reference clock is selected

IREFSTEN

Internal Reference Stop Enable — Controls whether the internal reference clock remains enabled when the

ICS enters stop mode.

1 Internal reference clock remains enabled in stop

0 Internal reference clock is disabled in stop

432

BDIV

Reset:

000

= Unimplemented

Figure 9-4. ICS Control Register 2 (ICSC2)

Table 9-3. ICSC2 Field Descriptions

Field

Description

7:6

BDIV

Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bit. This

controls the bus frequency.

00 Encoding 0 — Divides selected clock by 1

01 Encoding 1 — Divides selected clock by 2 (reset default)

10 Encoding 2 — Divides selected clock by 4

11 Encoding 3 — Divides selected clock by 8

Low Power Select — Controls whether the FLL is disabled in FLL bypassed modes.

FLL is disabled in bypass modes

FLL is not disabled in bypass mode

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