SC9RS08KA2 datasheet(80/134 Pages) FREESCALE

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Internal Clock Source (RS08ICSV1)

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

9.4

Functional Description

9.4.1

Operational Modes

The states of the ICS are shown as a state diagram and are described in this section. The arrows indicate

the allowed movements between the states.

Figure 9-7. Clock Switching Modes

9.4.1.1

FLL Engaged Internal (FEI)

FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when CLKS is

written to 0.

In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by

the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency.

9.4.1.2

FLL Bypassed Internal (FBI)

The FLL bypassed internal (FBI) mode is entered when CLKS is written to 1 and LP bit is a 0.

In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL

clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512

times the filter frequency.

9.4.1.3

FLL Bypassed Internal Low Power (FBILP)

The FLL bypassed internal low power (FBILP) mode is entered when CLKS is written to 1 and LP = 1.

In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock

and the FLL is disabled.

FLL Bypassed

Internal Low

Power(FBILP)

CLKS=0

1 ICS enters its Stop state when MCU enters stop, FLL is always disabled. ICS returns to the state that

was active before MCU entered stop, unless a reset occurs while in stop.

2 If IREFSTEN is set when MCU enters stop, the ICSIRCLK remains running.

FLL Engaged

Internal (FEI)

FLL Bypassed

Internal (FBI)

CLKS=1

LP=0

CLKS=1

LP=1

Stop1, 2

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