SC9RS08KA2 datasheet(19/134 Pages) FREESCALE

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Chapter 2 Pins and Connections

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

2.4.1

Power

VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O

buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated

lower-voltage source to the CPU and other internal circuitry of the MCU.

Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic

capacitor, such as a 10-

μF tantalum capacitor, to provide bulk charge storage for the overall system, and a

bypass capacitor, such as a 0.1-

μF ceramic capacitor, located as near to the MCU power pins as practical

to suppress high-frequency noise.

2.4.2

PTA2/KBIP2/TCLK/RESET/VPP

After a power-on reset (POR) into user mode, the PTA2/KBIP2/TCLK/RESET/VPP pin defaults to a

general-purpose input port pin, PTA2. Setting RSTPE in SOPT configures the pin to be the RESET input

pin. After configured as RESET, the pin will remain as RESET until the next POR. The RESET pin can

be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET

pin (RSTPE = 1), the internal pullup device is automatically enabled.

External VPP voltage (typically 12 V, see Section A.10, “FLASH Specifications”) is required on this pin

when performing Flash programming or erasing. The VPP connection is always connected to the internal

Flash module regardless of the pin function. To avoid over stressing the Flash, external VPP voltage must

be removed and voltage higher than VDD must be avoided when Flash programming or erasing is not

taking place.

NOTE

This pin does not contain a clamp diode to VDD and should not be driven

above VDD when Flash programming or erasing is not taking place.

2.4.3

PTA3/ACMPO/BKGD/MS

The background / mode select function is shared with an output-only pin on PTA3 pin and the optional

analog comparator output. While in reset, the pin functions as a mode select pin. Immediately after reset

rises, the pin functions as the background pin and can be used for background debug communication.

While functioning as a background / mode select pin, this pin has an internal pullup device enabled. To use

as an output-only port, BKGDPE in SOPT must be cleared.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.

If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low

during the power-on-reset, which forces the MCU to active background mode.

The BKGD pin is used primarily for background debug controller (BDC) communications using a custom

protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC

clock equals the bus clock rate; therefore, no significant capacitance should connected to the BKGD/MS

pin that could interfere with background serial communications.

Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol

provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from

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