SC9RS08KA2 datasheet(61/134 Pages) FREESCALE

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Chapter 8 Central Processor Unit (RS08CPUV1)

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

8.2.7

Page Select Register (PAGESEL)

This 8-bit page select register allows the user to access all memory locations in the entire

16K-byte address space through a page window located from $00C0 to $00FF. This register

resides at the memory mapped location $001F.

For details on the PAGESEL register, please refer to

the RS08 Core Reference Manual.

8.3

Addressing Modes

Whenever the MCU reads information from memory or writes information into memory, an addressing

mode is used to determine the exact address where the information is read from or written to. This section

explains several addressing modes and how each is useful in different programming situations.

Every opcode tells the CPU to perform a certain operation in a certain way. Many instructions, such as load

accumulator (LDA), allow several different ways to specify the memory location to be operated on, and

each addressing mode variation requires a separate opcode. All of these variations use the same instruction

mnemonic, and the assembler knows which opcode to use based on the syntax and location of the operand

field. In some cases, special characters are used to indicate a specific addressing mode (such as the #

[pound] symbol, which indicates immediate addressing mode). In other cases, the value of the operand

tells the assembler which addressing mode to use. For example, the assembler chooses short addressing

mode instead of direct addressing mode if the operand address is from $0000 to $001F. Besides allowing

the assembler to choose the addressing mode based on the operand address, assembler directives can also

be used to force direct or tiny/short addressing mode by using the “>” or “<” prefix before the operand,

respectively.

Some instructions use more than one addressing mode. For example, the move instructions use one

addressing mode to access the source value from memory and a second addressing mode to access the

destination memory location. For these move instructions, both addressing modes are listed in the

documentation. All branch instructions use relative (REL) addressing mode to determine the destination

for the branch, but BRCLR, BRSET, CBEQ, and DBNZ also must access a memory operand. These

instructions are classified by the addressing mode used for the memory operand, and the relative

addressing mode for the branch offset is assumed.

The discussion in the following paragraphs includes how each addressing mode works and the syntax clues

that instruct the assembler to use a specific addressing mode.

8.3.1

Inherent Addressing Mode (INH)

This addressing mode is used when the CPU inherently knows everything it needs to complete the

instruction and no addressing information is supplied in the source code. Usually, the operands that the

CPU needs are located in the CPU’s internal registers, as in LSLA, CLRA, INCA, SLA, RTS, and others.

A few inherent instructions, including no operation (NOP) and background (BGND), have no operands.

8.3.2

Relative Addressing Mode (REL)

Relative addressing mode is used to specify the offset address for branch instructions relative to the

program counter. Typically, the programmer specifies the destination with a program label or an

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