SC9RS08KA2 datasheet(102/134 Pages) FREESCALE

102 / 134 page

Chapter 12 Development Support

SC9RS08KA2 Series Data Sheet, Rev. 1

102

Freescale Semiconductor

Figure 12-5. BDM Target-to-Host Serial Bit Timing (Logic 0)

12.3.3

SYNC and Serial Communication Timeout

The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If

BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command

was issued. In this case, the target will keep waiting for a rising edge on BKGD to answer the SYNC

request pulse. If the rising edge is not detected, the target will keep waiting indefinitely, without any

timeout limit. When a rising edge on BKGD occurs after a valid SYNC request, the BDC will drive the

BKGD pin low for exactly 128 BDC cycles.

Consider now the case where the host returns BKGD to logic 1 before 128 cycles. This is interpreted as a

valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge

marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock

cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting

memory or the operating mode of the MCU. This is referred as a soft-reset to the BDC.

If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will

occur causing the command to be disregarded. The data is not available for retrieving after the timeout has

occurred. A soft-reset is also used to end a READ_BLOCK or WRITE_BLOCK command.

The following describes the actual bit-time requirements for a host to guarantee logic 1 or 0 bit

transmission without the target timing out or interpreting the bit as a SYNC command:

•

To send a logic 0, BKGD must be kept low for a minimum of 12 BDC cycles and up to 511 BDC

cycles except for the first bit of a command sequence, which will be detected as a SYNC request.

•

To send a logic 1, BKGD must be held low for at least four BDC cycles, be released by the eighth

cycle, and be held high until at least the sixteenth BDC cycle.

10 CYCLES

BDC CLOCK

(TARGET MCU)

HOST DRIVE

TO BKGD PIN

TARGET MCU

DRIVE AND

PERCEIVED START

OF BIT TIME

HIGH IMPEDANCE

BKGD PIN

10 CYCLES

SPEEDUP PULSE

SPEEDUP

PULSE

EARLIEST START

OF NEXT BIT

HOST SAMPLES BKGD PIN

SC9RS08KA2 датащи(PDF) 102 Page - Freescale Semiconductor, Inc

SC9RS08KA2 датащи(HTML) 102 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL