H838532H datasheet(111/508 Pages) RENESAS

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Section 4 Clock Pulse Generators

Rev. 1.00 May 30, 2008 Page 91 of 484

REJ09B0436-0100

4.4

Prescalers

This LSI is equipped with two on-chip prescalers having different input clocks (prescaler S and

prescaler W). Prescaler S is a 13-bit counter using the system clock (

φ) as its input clock. Its

prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a

5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (

W/4) as its input clock. Its

prescaled outputs are used by timer A as a time base for timekeeping.

(1) Prescaler S (PSS)

Prescaler S is a 13-bit counter using the system clock (

φ) as its input clock. It is incremented once

per clock period.

Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.

In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse

generator stops. Prescaler S also stops and is initialized to H'0000.

The CPU cannot read or write prescaler S.

The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI3-1, SC3-2, the

A/D converter, the LCD controller, the watchdog timer, and the 14-bit PWM. The divider ratio

can be set separately for each on-chip peripheral function.

In active (medium-speed) mode the clock input to prescaler S is

φosc/16, φosc/32, φosc/64, or

φosc/128.

(2) Prescaler W (PSW)

Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (

W/4) as its input

clock.

Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.

Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues

functioning so long as clock signals are supplied to pins X1 and X2.

Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).

Output from prescaler W can be used to drive timer A, in which case timer A functions as a time

base for timekeeping.

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