APEX20KC datasheet(36/90 Pages) ALTERA

36 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

f For more information on APEX 20KC devices and CAM, see Application

Note 119 (Implementing High-Speed Search Applications with APEX CAM).

Driving Signals to the ESB

ESBs provide flexible options for driving control signals. Different clocks

can be used for the ESB inputs and outputs. Registers can be inserted

independently on the data input, data output, read address, write

address, WE, and RE signals. The global signals and the local interconnect

can drive the WE and RE signals. The global signals, dedicated clock pins,

and local interconnect can drive the ESB clock signals. Because the LEs

drive the local interconnect, the LEs can control the WE and RE signals and

the ESB clock, clock enable, and asynchronous clear signals. Figure 24

shows the ESB control signal generation logic.

Figure 24. ESB Control Signal Generation

An ESB is fed by the local interconnect, which is driven by adjacent LEs

(for high-speed connection to the ESB) or the MegaLAB interconnect. The

ESB can drive the local, MegaLAB, or FastTrack interconnect routing

structure to drive LEs and IOEs in the same MegaLAB structure or

anywhere in the device.

RDEN

WREN

INCLOCK

INCLKENA

OUTCLOCK

OUTCLKENA

Dedicated

Clocks

Global

Signals

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

INCLR

OUTCLR

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