APEX20KC datasheet(17/90 Pages) ALTERA

номер детали	APEX20KC

подробное описание детали	Programmable Logic Device

PDF	90 Pages

Scroll/Zoom	100%

производитель	ALTERA [Altera Corporation]

домашняя страница	http://www.altera.com

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17 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 8. APEX 20KC LE Operating Modes

Notes to Figure 8:

(1)

LEs in normal mode support register packing.

(2)

There are two LAB-wide clock enables per LAB.

(3)

When using the carry-in in normal mode, the packed register feature is unavailable.

(4)

A register feedback multiplexer is available on LE1 of each LAB.

(5)

The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for

LEs other than the second LE in an LAB.

(6)

The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.

PRN

CLRN

4-Input

LUT

Carry-In

(3)

Cascade-Out

Cascade-In

LE Out

Normal Mode (1)

PRN

CLRN

Cascade-Out

Cascade-In

3-Input

LUT

Carry-In

3-Input

LUT

Carry-Out

Arithmetic Mode

Counter Mode

data1

(5)

data2

(5)

PRN

CLRN

Carry-In

LUT

3-Input

LUT

Carry-Out

data3 (data)

Cascade-Out

Cascade-In

LAB-Wide

Synchronous

Load

(6)

LAB-Wide

Synchronous

Clear

(6)

(4)

LE Out

ENA

LAB-Wide

Clock Enable

(2)

ENA

LAB-Wide

Clock Enable

(2)

ENA

LAB-Wide

Clock Enable

(2)

data1

data2

data1

data2

data3

data4

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