APEX20KC datasheet(29/90 Pages) ALTERA

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Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

ESBs can implement synchronous RAM, which is easier to use than

asynchronous RAM. A circuit using asynchronous RAM must generate

the RAM write enable (WE) signal, while ensuring that its data and address

signals meet setup and hold time specifications relative to the WE signal.

In contrast, the ESB’s synchronous RAM generates its own WE signal and

is self-timed with respect to the global clock. Circuits using the ESB’s self-

timed RAM must only meet the setup and hold time specifications of the

global clock.

ESB inputs are driven by the adjacent local interconnect, which in turn can

be driven by the FastTrack or MegaLAB interconnect. Because the ESB can

be driven by the local interconnect, an adjacent LE can drive it directly for

fast memory access. ESB outputs drive the FastTrack and MegaLAB

interconnects. In addition, ten ESB outputs, nine of which are unique

output lines, drive the local interconnect for fast connection to adjacent

LEs or for fast feedback product-term logic.

When implementing memory, each ESB can be configured in any of the

following sizes: 128 × 16, 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1. By

combining multiple ESBs, the Quartus II software implements larger

memory blocks automatically. For example, two 128 × 16 RAM blocks can

be combined to form a 128 × 32 RAM block, and two 512 × 4 RAM blocks

can be combined to form a 512 × 8 RAM block. Memory performance does

not degrade for memory blocks up to 2,048 words deep. Each ESB can

implement a 2,048-word-deep memory; the ESBs are used in parallel,

eliminating the need for any external control logic and its associated

delays.

To create a high-speed memory block that is more than 2,048 words deep,

ESBs drive tri-state lines. Each tri-state line connects all ESBs in a column

of MegaLAB structures, and drives the MegaLAB interconnect and row

and column FastTrack interconnect throughout the column. Each ESB

incorporates a programmable decoder to activate the tri-state driver

appropriately. For instance, to implement 8,192-word-deep memory, four

ESBs are used. Eleven address lines drive the ESB memory, and two more

drive the tri-state decoder. Depending on which 2,048-word memory

page is selected, the appropriate ESB driver is turned on, driving the

output to the tri-state line. The Quartus II software automatically

combines ESBs with tri-state lines to form deeper memory blocks. The

internal tri-state control logic is designed to avoid internal contention and

floating lines. See Figure 18.

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