APEX20KC datasheet(33/90 Pages) ALTERA

номер детали	APEX20KC

подробное описание детали	Programmable Logic Device

PDF	90 Pages

Scroll/Zoom	100%

производитель	ALTERA [Altera Corporation]

домашняя страница	http://www.altera.com

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33 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Single-Port Mode

The APEX 20KC ESB also supports a single-port mode, which is used

when simultaneous reads and writes are not required. See Figure 22.

Figure 22. ESB in Single-Port Mode

Note (1)

Note toFigure 22:

(1)

All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.

Content-Addressable Memory

In APEX 20KC devices, the ESB can implement CAM. CAM can be

thought of as the inverse of RAM. When read, RAM outputs the data for

a given address. Conversely, CAM outputs an address for a given data

word. For example, if the data FA12 is stored in address 14, the CAM

outputs 14 when FA12 is driven into it.

Dedicated Clocks

ENA

data[ ]

address[ ]

RAM/ROM

128

× 16

256

× 8

512

× 4

1,024

× 2

2,048

× 1

Data In

Address

Write Enable

Data Out

outclken

inclken

inclock

outclock

Write

Pulse

Generator

wren

Dedicated Inputs &

Global Signals

To MegaLAB,

FastTrack &

Local

Interconnect

APEX20KC датащи(PDF) 33 Page - Altera Corporation

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