APEX20KC datasheet(51/90 Pages) ALTERA

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APEX 20KC Programmable Logic Device Data Sheet

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

All APEX 20KC devices provide JTAG BST circuitry that complies with

the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can

be performed before or after configuration, but not during configuration.

APEX 20KC devices can also use the JTAG port for configuration with the

Quartus II software or with hardware using either Jam Files (.jam) or Jam

Byte-Code Files (.jbc). Finally, APEX 20KC devices use the JTAG port to

monitor the logic operation of the device with the SignalTap embedded

logic analyzer. APEX 20KC devices support the JTAG instructions shown

in Table 13.

Table 13. APEX 20KC JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern to be output at the device pins.

Also used by the SignalTap embedded logic analyzer.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a test

pattern at the output pins and capturing test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data

to pass synchronously through selected devices to adjacent devices during normal device

operation.

USERCODE

Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,

allowing the USERCODE to be serially shifted out of TDO.

IDCODE

Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE

to be serially shifted out of TDO.

ICR Instructions

Used when configuring an APEX 20KC device via the JTAG port with a MasterBlasterTM

or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File via

an embedded processor.

SignalTap

Instructions

Monitors internal device operation with the SignalTap embedded logic analyzer.

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