APEX20KC datasheet(24/90 Pages) ALTERA

номер детали	APEX20KC

подробное описание детали	Programmable Logic Device

PDF	90 Pages

Scroll/Zoom	100%

производитель	ALTERA [Altera Corporation]

домашняя страница	http://www.altera.com

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24 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Product-Term Logic

The product-term portion of the MultiCore architecture is implemented

with the ESB. The ESB can be configured to act as a block of macrocells on

an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local

interconnect; therefore, it can be driven by the MegaLAB interconnect or

the adjacent LAB. Also, nine ESB macrocells feed back into the ESB

through the local interconnect for higher performance. Dedicated clock

pins, global signals, and additional inputs from the local interconnect

drive the ESB control signals.

In product-term mode, each ESB contains 16 macrocells. Each macrocell

consists of two product terms and a programmable register. Figure 13

shows the ESB in product-term mode.

Table 8. APEX 20KC Routing Scheme

Source

Destination

Row

I/O Pin

Column

I/O Pin

ESB

Local

Interconnect

MegaLAB

Interconnect

Row

FastTrack

Interconnect

Column

FastTrack

Interconnect

FastRow

Interconnect

Row I/O pin

vvvv

Column I/O

vvvv

ESB

vvvv

Local

interconnect

MegaLAB

interconnect

Row

FastTrack

interconnect

Column

FastTrack

interconnect

FastRow

interconnect

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