APEX20KC datasheet(46/90 Pages) ALTERA

46 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Open-drain output pins on APEX 20KC devices (with a series resistor and

a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins

that require a VIH of 3.5 V. When the pin is inactive, the trace will be pulled

up to 5.0 V by the resistor. The open-drain pin will only drive low or tri-

state; it will never drive high. The rise time is dependent on the value of

the pull-up resistor and load impedance. The IOL current specification

should be considered when selecting a pull-up resistor.

ClockLock &

ClockBoost

Features

APEX 20KC devices support the ClockLock and ClockBoost clock

management features, which are implemented with PLLs. The ClockLock

circuitry uses a synchronizing PLL that reduces the clock delay and skew

within a device. This reduction minimizes clock-to-output and setup

times while maintaining zero hold times. The ClockBoost circuitry, which

provides a clock multiplier, allows the designer to enhance device area

efficiency by sharing resources within the device. The ClockBoost

circuitry allows the designer to distribute a low-speed clock and multiply

that clock on-device. APEX 20KC devices include a high-speed clock tree;

unlike ASICs, the user does not have to design and optimize the clock tree.

The ClockLock and ClockBoost features work in conjunction with the

APEX 20KC device’s high-speed clock to provide significant

improvements in system performance and bandwidth. APEX 20KC

devices in -7 and -8 speed grades have PLLs and support the ClockLock

and ClockBoost features.

The ClockLock and ClockBoost features in APEX 20KC devices are

enabled through the Quartus II software. External devices are not

required to use these features.

APEX 20KC ClockLock Feature

APEX 20KC devices include up to four PLLs, which can be used

independently. Two PLLs are designed for either general-purpose use or

LVDS use (on devices that support LVDS I/O pins). The remaining two

PLLs are designed for general-purpose use. The EP20K200C devices have

two PLLs; the EP20K400C and larger devices have four PLLs.

The following sections describe some of the features offered by the

APEX 20KC PLLs.

External PLL Feedback

The ClockLock circuit’s output can be driven off-chip to clock other

devices in the system; further, the feedback loop of the PLL can be routed

off-chip. This feature allows the designer to exercise fine control over the

I/O interface between the APEX 20KC device and another high-speed

device, such as SDRAM.

APEX20KC датащи(PDF) 46 Page - Altera Corporation

APEX20KC датащи(HTML) 46 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

датащи скачать

ссылки URL