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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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APEX20KC датащи(PDF) 27 Page - Altera Corporation |
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APEX20KC датащи(HTML) 27 Page - Altera Corporation |
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27 / 90 page  Altera Corporation 27 APEX 20KC Programmable Logic Device Data Sheet The programmable register also supports an asynchronous clear function. Within the ESB, two asynchronous clears are generated from global signals and the local interconnect. Each macrocell can either choose between the two asynchronous clear signals or choose to not be cleared. Either of the two clear signals can be inverted within the ESB. Figure 15 shows the ESB control logic when implementing product-terms. Figure 15. ESB Product-Term Mode Control Logic Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 32 product terms to feed the macrocell OR logic directly, with two product terms provided by the macrocell and 30 parallel expanders provided by the neighboring macrocells in the ESB. The Quartus II Compiler can allocate up to 15 sets of up to two parallel expanders per set to the macrocells automatically. Each set of two parallel expanders incurs a small, incremental timing delay. Figure 16 shows the APEX 20KC parallel expanders. CLK2 CLKENA2 CLK1 CLKENA1 CLR2 CLR1 Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect 4 4 |
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