APEX20KC datasheet(35/90 Pages) ALTERA

35 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 23. APEX 20KC CAM Block Diagram

CAM can be used in any application requiring high-speed searches, such

as networking, communications, data compression, and cache

management.

The APEX 20KC on-chip CAM provides faster system performance than

traditional discrete CAM. Integrating CAM and logic into the APEX 20KC

device eliminates off-chip and on-chip delays, improving system

performance.

When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or

deeper CAM can be implemented by combining multiple CAMs with

some ancillary logic implemented in LEs. The Quartus II software

combines ESBs and LEs automatically to create larger CAMs.

CAM supports writing “don’t care” bits into words of the memory. The

“don’t care” bit can be used as a mask for CAM comparisons; any bit set

to “don’t care” has no effect on matches.

The output of the CAM can be encoded or unencoded. When encoded, the

ESB outputs an encoded address of the data’s location. For instance, if the

data is located in address 12, the ESB output is 12. When unencoded, the

ESB uses its 16 outputs to show the location of the data over two clock

cycles. In this case, if the data is located in address 12, the 12th output line

goes high. When using unencoded outputs, two clock cycles are required

to read the output because a 16-bit output bus is used to show the status

of 32 words.

The encoded output is better suited for designs that ensure duplicate data

is not written into the CAM. If duplicate data is written into two locations,

the CAM’s output will be incorrect. If the CAM may contain duplicate

data, the unencoded output is a better solution; CAM with unencoded

outputs can distinguish multiple data locations.

CAM can be pre-loaded with data during configuration, or it can be

written during system operation. In most cases, two clock cycles are

required to write each word into CAM. When “don’t care” bits are used,

a third clock cycle is required.

wraddress[]

data[]

wren

inclock

inclocken

inaclr

data_address[]

match

outclock

outclocken

outaclr

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