MPF0900AMMA2ES datasheet(130/205 Pages) NXP

130 / 205 page

NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

VMONx_RUN[4:0] VMONx_STBY[4:0]

VMONx monitoring voltage

11110

1.2500 V

11111

1.2750 V

Table 171. VMONx monitoring voltage configuration bits...continued

In applications where the monitored outputs require dynamic voltage scaling during the system operation, the

MCU must manage the voltage transitions in a safe way at the system level.

In order to manage dynamic transition of the external voltage, the VMONx block provides a programmable

masking timer to prevent OV/UV conditions from happening during the external voltage transition.

When the VMONx voltage selection is changed from one set point to another, the VMONx masks the OV and

UV fault monitoring for a period of time defined by the VMONx_TMASK[1:0] bits. The default value for the

masking timer is set in OTP registers via the OTP_VMONx_TMASK[1:0] bits.

VMONx_TMASK[1:0]

VMONx masking timer

500 µs

1000 µs

2000 µs

5000 µs

Table 172. VMONx masking timer configuration bits

Because the PF09 does not have control over the DVS transition of the external supply, the MCU must first

request a change on the VMON set point and then start the voltage transition on the external voltage supply

directly afterwards. The system designer must take communication delays, as well as voltage slew rates, into

consideration when selecting the masking time for the VMONx.

The external voltage monitoring pins can also perform monitoring of larger voltage levels by providing an

external resistor divider to divide the output voltage to a lower input level suitable to the VMONx pin. The

external resistive voltage divider must be calculated in such way that the resulting voltage matches the selected

voltage reference set in the VMONx_RUN[4:0] and VMONx_STBY[4:0] bits.

The formula to calculate the resistor divider is described in Figure 33:

aaa-056076

VREF =

VLDOx_RUN/VLDOx_STBY

= Fixed

= R2 (Vx - VREF)/VREF

Figure 33. External VMON resistor divider calculation

When using an external resistive voltage divider, no DVS operation is supported on the monitored signal. R2

must be selected between 1 kΩ and100 kΩ and resistor accuracy should be rated 1 % or better to minimize

overall monitoring accuracy fallouts.

When the VMONx is not enabled by default in the Power-up sequence, the monitoring block can be enabled

manually via the VMONx_EN bit after the external supply has been enabled and is ready to be monitored.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

Document feedback

130 / 205

MPF0900AMMA2ES датащи(PDF) 130 Page - NXP Semiconductors

MPF0900AMMA2ES датащи(HTML) 130 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL