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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPF0900AMMA2ES датащи(PDF) 109 Page - NXP Semiconductors |
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MPF0900AMMA2ES датащи(HTML) 109 Page - NXP Semiconductors |
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109 / 205 page  NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring All parameters are specified at TA = -40 °C to 125 °C, VSWxIN = VIN = UVDET to 5.5 V, VSWxFB = 1.0 V, ISWx = 0.5 A, typical external component values, fSW = 2.5 MHz, unless otherwise noted. Typical values are characterized at VSWxIN = 5.0 V, VSWxFB = 1.0 V, ISWx = 0.5 A, and TA = 25 °C, unless otherwise noted. Symbol Description Min Typ Max Unit tPFM2PWM_SWx PFM to PWM transition time 10 – 50 µs RDS25_SWxHS High-side FET RDSON[2] • TJ = 25°C • Including bond-wire and package resistance – 60 – mΩ RDS125_SWxHS High-side FET RDSON[2] • TJ = 125°C • Including bond-wire and package resistance – 75 – mΩ RDS25_SWxLS Low-side FET RDSON[3] • TJ = 25°C • Including bond-wire and package resistance – 32 – mΩ RDS125_SWxLS Low-side FET RDSON[3] • TJ = 125°C • Including bond-wire and package resistance – 42 – mΩ RDIS_SWx Discharge-resistance • Regulator disabled and ramp completed 20 60 100 Ω Table 138. SW2 - SW5 electrical characteristics...continued [1] UVDET represents the minimum functional level for the PF09; VSW1IN must meet the minimum headroom to ensure proper output voltage regulation. [2] Typical high-side FET resistance due to packaging (bondwire + metal) at room temp is 24 mΩ. [3] Typical low-side FET resistance due to packaging (bondwire + metal) at room temp is 21 mΩ. Symbol Description Min Typ Max Units L Output inductor • Nominal inductor DC resistance < 24 mΩ • Minimum saturation current at full load: 5.5 A – 0.47 – µH COUT Effective output capacitance • x 22 μF, 6.3 V • Low ESR ceramic capacitor. 22 44 300 µF CIN Input capacitor • 4.7 μF, 10 V • Low ESR ceramic capacitor 4.23 4.7 5.17 µF Table 139. SWx recommended external components. 13.2.4 LDO1 (500 mA linear regulator with load switch mode) LDO1 is a low dropout linear regulator with 500 mA current capability and input voltage range from 1.8 V to 5.5 V. It provides programmable output voltage between 0.75 V and 3.3 V, with up to 2 % output voltage accuracy. The LDO1 output implements a configurable soft-start ramp control during power up (enable) and discharge mechanism during power down (disable). The LDO1_RUN_EN bit is provided to enable or disabled the LDO1 output during the RUN state. The LDO1_RUN_EN bit will be set to 1 by default, if the LDO is enabled in the Power-up sequence, or 0 if it is disabled at power up. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 109 / 205 |
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