MPF0900AMMA2ES datasheet(150/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

WD_DURATION[3:0]

Watchdog timer duration

1011

2048 ms

1100

4096 ms

1101

8192 ms

1110

16384 ms

1111

32768 ms

Table 196. System watchdog timer configuration bits...continued

At power up, the WD timer will start counting only after the RSTB pin is released in the Power-up sequence.

The default value of the WD_DURATION[3:0] bits is set on OTP by the OTP_WD_DURATION[3:0] bits.

The system can define a longer timer duration at power up, to allow the MCU to perform its booting sequence,

and then reduce the timer duration to ensure a fault detection within the required system FTTI. When the

WD_DURATION[3:0] bits are changed during the SYSTEM ON states, the WD timer will be restarted to ensure

the system is properly synchronized with the MCU.

The OTP_WD_WINDOW[1:0] bits are provided to select the close/open ratio to service the system watchdog.

OTP_WD_WINDOW[1:0]

Close window

Open window

0 %

100 %

25 %

75 %

50 %

75 %

25 %

Table 197. System watchdog window configuration bits

When OTP_WD_WINDOW = 00, the device will use 100 % of the WD_DURATION as an open window to

service the WD. Any other selection will close the watchdog window for the first part of the timer and open the

window for the second part of the timer. Servicing the watchdog within the closed window, or failing to service

the WD within the watchdog duration, will be interpreted as a bad watchdog refresh.

The WD_NOK_CNT[2:0] counter is provided to count WD_NOK events, in order to be able to generate a PMIC

reset event if a fault condition is present on the MCU. The WD_NOK_CNT counter uses a 2-by-1 count strategy

to ensure the system is not caught in a software loop that is able to service one good WD per each bad WD

within the loop.

• An invalid response will increase the WD_NOK_CNT[2:0] by 2

• A valid response will decrease the WD_NOK_CNT[2:0] by 1

If WD_NOK_CNT[2:0] = WD_NOK_MAX[2:0], the device will generate a hard reset event and the

RESET_CNT[3:0] bits will be increased by 1. Refer to section 16.4.2 Reset Conditions, for a detailed description

of the reset behavior.

The initial value for the WD_NOK_MAX[2:0] is set in the OTP by the OTP_WD_NOK_MAX[2:0] bits.

The WD_NOK_CNT counter uses a 2-by-1 count strategy to ensure the system is not caught in a software loop

that is able to service one good WD per each bad WD within the loop.

• An invalid response will increase the WD_NOK_CNT[2:0] by 2

• A valid response will decrease the WD_NOK_CNT[2:0] by 1

Due to the 2-by-1 design of the watchdog counter, when the WD_NOK_MAX[2:0] is set to 0x01 or 0x02, a WD

reset event will be initiated as soon as the first bad WD refresh occurs.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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