STM32H533CE datasheet(185/231 Pages) STMICROELECTRONICS

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DS14539 Rev 1

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STM32H533xx

Electrical characteristics

200

5.3.30

Timer characteristics

The parameters given in Table 104 are guaranteed by design.

Refer to Section 5.3.14 for details on the input/output alternate function characteristics

(output compare, input capture, external clock, PWM output).

IINRUSH

Control of

maximum DC

current drive on

VREFBUF_OUT

during startup

phase(4)(4)

IDDA(VREF

BUF)

VREFBUF

consumption from

VDDA

ILOAD = 0 µA

µA

ILOAD = 500 µA

ILOAD = 4 mA

1. Specified by design - Not tested in production, unless otherwise specified.

2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).

3. Evaluated by characterization - Not tested in production.

4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in

the range of 2.1 V - 3.6 V, 2.4 V -3.6 V and 2.8 V - 3.6 V for VRS = 010, 001, and 000, respectively.

Table 103. VREFBUF characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 104. TIMx characteristics(1)(2)

Symbol

Parameter

Conditions(3)

Min

Max

Unit

tres(TIM)

Timer resolution time

AHB/APBx prescaler = 1, 2, or 4,

fTIMxCLK = 250 MHz

tTIMxCLK

AHB/APBx prescaler > 4,

fTIMxCLK = 125 MHz

tTIMxCLK

fEXT

Timer external clock

frequency on CH1 to CH4

fTIMxCLK = 250 MHz

fTIMxCLK / 2

MHz

ResTIM

Timer resolution

16 / 32

bit

tMAX_COUNT

Maximum possible count

with 32-bit counter

65536 ×

65536

tTIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.

2. Specified by design - Not tested in production.

3. The maximum timer frequency on APB1 or APB2 is up to 250 MHz, by setting the TIMPRE bit in the RCC_CFGR register,

if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1,

otherwise TIMxCLK = 4 x Frcc_pclkx1 or TIMxCLK = 4 x Frcc_pclkx2.

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