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STM32H533CE датащи(PDF) 188 Page - STMicroelectronics |
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STM32H533CE датащи(HTML) 188 Page - STMicroelectronics |
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188 / 231 page ![]() Electrical characteristics STM32H533xx 188/231 DS14539 Rev 1 Figure 47. USART timing diagram in Master mode 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 48. USART timing diagram in Slave mode th(TX) Data output hold time Slave mode 7.5 - - ns Master mode 0 - - 1. Evaluated by characterization - Not tested in production. 2. For PB14 with OSPEEDRy[1:0] = 01. 3. Tker is the usart_ker_ck_pres clock period. Table 107. USART characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit MSv65386V4 CPHA = 0 TX OUTPUT RX INPUT CPHA = 0 LSB OUT LSB IN CPOL = 0 CPOL = 1 BIT1 OUT 1/fCK tw(CKH) tw(CKL) th(RX) CPHA = 1 CPHA = 1 CPOL = 0 CPOL = 1 tsu(RX) tv(TX) th(TX) MSB IN BIT6 IN MSB OUT MSv65387V4 NSS input CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 TX output RX input tsu(RX) th(RX) tw(CKL) tw(CKH) 1/fCK th(NSS) tsu(NSS) tv(TX) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(TX) Last bit IN |
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