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MSP430 датащи(PDF) 13 Page - Texas Instruments |
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MSP430 датащи(HTML) 13 Page - Texas Instruments |
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13 / 96 page ![]() 13 MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203 www.ti.com SLAS734G – APRIL 2011 – REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Specifications Copyright © 2011–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. (3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5 Specifications 5.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Voltage applied at VCC to VSS –0.3 4.1 V Voltage applied to any pin(2) –0.3 VCC + 0.3 V Diode current at any device pin ±2 mA Storage temperature, Tstg (3) Unprogrammed device –55 150 °C Programmed device –55 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. 5.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250 (1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency. (2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. 5.3 Recommended Operating Conditions Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage During program execution 1.8 3.6 V During flash programming or erase 2.2 3.6 VSS Supply voltage 0 V TA Operating free-air temperature –40 85 °C fSYSTEM Processor frequency (maximum MCLK frequency using the USART module)(1)(2) VCC = 1.8 V, Duty cycle = 50% ±10% DC 6 MHz VCC = 2.7 V, Duty cycle = 50% ±10% DC 12 VCC = 3.3 V, Duty cycle = 50% ±10% DC 16 |
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