MSP430 datasheet(10/96 Pages) TI2

10 / 96 page

MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G – APRIL 2011 – REVISED APRIL 2016

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Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

MSP430G2203

Terminal Configuration and Functions

(1)

MSP430G2x33 devices only

4.2

Signal Descriptions

Table 4-1 describes the signals.

Table 4-1. Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PW20,

N20

PW28

RHB32

P1.0/

I/O

General-purpose digital I/O pin

TA0CLK/

Timer0_A, clock signal TACLK input

ACLK/

ACLK signal output

ADC10 analog input A0(1)

P1.1/

I/O

General-purpose digital I/O pin

TA0.0/

Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit

UCA0RXD/

USCI_A0 receive data input in UART mode

UCA0SOMI/

USCI_A0 slave data out/master in SPI mode

ADC10 analog input A1(1)

P1.2/

I/O

General-purpose digital I/O pin

TA0.1/

Timer0_A, capture: CCI1A input, compare: Out1 output

UCA0TXD/

USCI_A0 transmit data output in UART mode

UCA0SIMO/

USCI_A0 slave data in/master out in SPI mode

ADC10 analog input A2(1)

P1.3/

I/O

General-purpose digital I/O pin

ADC10CLK/

ADC10, conversion clock output(1)

A3/

ADC10 analog input A3(1)

VREF-/VEREF-

ADC10 negative reference voltage (1)

P1.4/

I/O

General-purpose digital I/O pin

SMCLK/

SMCLK signal output

UCB0STE/

USCI_B0 slave transmit enable

UCA0CLK/

USCI_A0 clock input/output

A4/

ADC10 analog input A4(1)

VREF+/VEREF+

ADC10 positive reference voltage(1)

TCK

JTAG test clock, input terminal for device programming and test

P1.5/

I/O

General-purpose digital I/O pin

TA0.0/

Timer0_A, compare: Out0 output / BSL receive

UCB0CLK/

USCI_B0 clock input/output

UCA0STE/

USCI_A0 slave transmit enable

A5/

ADC10 analog input A5(1)

TMS

JTAG test mode select, input terminal for device programming and test

P1.6/

I/O

General-purpose digital I/O pin

TA0.1/

Timer0_A, compare: Out1 output

A6/

ADC10 analog input A6(1)

UCB0SOMI/

USCI_B0 slave out/master in SPI mode,

UCB0SCL/

USCI_B0 SCL I2C clock in I2C mode

TDI/TCLK

JTAG test data input or test clock input during programming and test

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