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MSP430 датащи(PDF) 56 Page - Texas Instruments |
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MSP430 датащи(HTML) 56 Page - Texas Instruments |
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56 / 96 page ![]() P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P2.3/TA1.0 P2.4/TA1.2 P2.5/TA1.2 From Timer Direction 0: Input 1: Output To Module PxOUT.y DVSS DVCC 1 TAx.y TAxCLK 1 0 PxIN.y EN D PxSEL.y PxREN.y 1 0 PxSEL2.y 1 0 PxSEL.y 1 3 2 1 0 PxSEL2.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y PxDIR.y 1 0 PxSEL.y 0 56 MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203 SLAS734G – APRIL 2011 – REVISED APRIL 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated 6.10.5 Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger Figure 6-10 shows the port diagram. Table 6-20 summarizes the selection of the pin functions. Figure 6-10. Port P2 (P2.0 to P2.5) Diagram |
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