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MSP430 датащи(PDF) 3 Page - Texas Instruments |
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MSP430 датащи(HTML) 3 Page - Texas Instruments |
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3 / 96 page ![]() Clock System Brownout Protection RST/NMI DVCC DVSS MCLK Watchdog WDT+ 15-Bit Timer0_A3 3 CC registers 16-MHz CPU including 16 registers Emulation 2BP JTAG interface SMCLK ACLK Port P1 8 I/Os, interrupt capability, pullup or pulldown resistors P1.x 8 P2.x Port P2 8 I/Os, interrupt capability, pullup or pulldown resistors Spy-Bi- Wire Timer1_A3 3 CC registers XIN XOUT Port P3 8 I/Os, pullup or pulldown resistors P3.x 8 8 RAM 256B Flash 8KB 4KB 2KB USCI A0 UART, LIN, IrDA, SPI USCI B0 SPI, I C 2 MDB MAB Copyright © 2016, Texas Instruments Incorporated 3 MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203 www.ti.com SLAS734G – APRIL 2011 – REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Device Overview Copyright © 2011–2016, Texas Instruments Incorporated Figure 1-2 shows the functional block diagram of the MSP430G2x03 MCUs. NOTE: Port P3 is available on 28-pin and 32-pin devices only. Figure 1-2. Functional Block Diagram, MSP430G2x03 |
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