MSP430 datasheet(39/96 Pages) TI2

39 / 96 page

MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

www.ti.com

SLAS734G – APRIL 2011 – REVISED APRIL 2016

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Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

MSP430G2203

Detailed Description

(1)

A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges.

(2)

Multiple source flags

(3)

(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4)

Interrupt flags are in the module.

(5)

In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

(6)

In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

(7)

This location is used as bootloader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)

disables the erasure of the flash if an invalid password is supplied.

(8)

The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

6.4

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFC0h (see

Table 6-3). The vector contains the 16-bit address of the appropriate interrupt handler instruction

sequence.

If the reset vector (at address 0FFFEh) contains 0FFFFh (for example, if the flash is not programmed), the

CPU goes into LPM4 immediately after power-up.

Table 6-3. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM

INTERRUPT

WORD

ADDRESS

PRIORITY

Power up

External reset

Watchdog Timer+

Flash key violation

PC out of range(1)

PORIFG

RSTIFG

WDTIFG

KEYV(2)

Reset

0FFFEh

31, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

ACCVIFG(2)

(non)-maskable(3)

(non)-maskable

0FFFCh

Timer1_A3

TACCR0 CCIFG(4)

maskable

0FFFAh

Timer1_A3

TACCR2 TACCR1 CCIFG, TAIFG(2)(4)

maskable

0FFF8h

0FFF6h

Watchdog Timer+

WDTIFG

maskable

0FFF4h

Timer0_A3

TACCR0 CCIFG(4)

maskable

0FFF2h

Timer0_A3

TACCR2 TACCR1 CCIFG, TAIFG

(5) (4)

maskable

0FFF0h

USCI_A0, USCI_B0 receive

USCI_B0 I2C status

UCA0RXIFG, UCB0RXIFG(2)(5)

maskable

0FFEEh

USCI_A0, USCI_B0 transmit

USCI_B0 I2C receive or transmit

UCA0TXIFG, UCB0TXIFG (2)(6)

maskable

0FFECh

ADC10

(MSP430G2x33 only)

ADC10IFG(4)

maskable

0FFEAh

0FFE8h

I/O Port P2 (up to eight flags)

P2IFG.0 to P2IFG.7(2)(4)

maskable

0FFE6h

I/O Port P1 (up to eight flags)

P1IFG.0 to P1IFG.7(2)(4)

maskable

0FFE4h

0FFE2h

0FFE0h

See (7)

0FFDEh

See (8)

0FFDEh to

0FFC0h

14 to 0, lowest

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