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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSP430 датащи(PDF) 28 Page - Texas Instruments |
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MSP430 датащи(HTML) 28 Page - Texas Instruments |
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28 / 96 page  t SU,MI t HD,MI UCLK SOMI SIMO t VALID,MO CKPL = 0 CKPL = 1 1/f UCxCLK t HD,MO t LO/HI t LO/HI t SU,MI t HD,MI UCLK SOMI SIMO t VALID,MO t HD,MO CKPL = 0 CKPL = 1 t LO/HI t LO/HI 1/f UCxCLK 28 MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203 SLAS734G – APRIL 2011 – REVISED APRIL 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Specifications Copyright © 2011–2016, Texas Instruments Incorporated (1) The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz. (2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. 5.25 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fUSCI USCI input clock frequency SMCLK, duty cycle = 50% ±10% fSYSTEM MHz fmax,BITCLK Maximum BITCLK clock frequency (equals baud rate in MBaud)(1) 3 V 2 MHz tτ UART receive deglitch time(2) 3 V 50 100 600 ns 5.26 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16 and Figure 5-17) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT fUSCI USCI input clock frequency SMCLK, duty cycle = 50% ±10% fSYSTEM MHz tSU,MI SOMI input data setup time 3 V 75 ns tHD,MI SOMI input data hold time 3 V 0 ns tVALID,MO SIMO output data valid time UCLK edge to SIMO valid, CL = 20 pF 3 V 20 ns Figure 5-16. SPI Master Mode, CKPH = 0 Figure 5-17. SPI Master Mode, CKPH = 1 |
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