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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSP430 датащи(PDF) 40 Page - Texas Instruments |
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MSP430 датащи(HTML) 40 Page - Texas Instruments |
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40 / 96 page  40 MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203 SLAS734G – APRIL 2011 – REVISED APRIL 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated 6.5 Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw Bit can be read and written. rw-0, rw-1 Bit can be read and written. It is reset or set by PUC. rw-(0), rw-(1) Bit can be read and written. It is reset or set by POR. SFR bit is not present in device. Figure 6-2. Interrupt Enable Register 1 (Address = 00h) 7 6 5 4 3 2 1 0 ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 Table 6-4. Interrupt Enable Register 1 Description Bit Field Type Reset Description 5 ACCVIE RW 0h Flash access violation interrupt enable 4 NMIIE RW 0h (Non)maskable interrupt enable 1 OFIE RW 0h Oscillator fault interrupt enable 0 WDTIE RW 0h Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Figure 6-3. Interrupt Enable Register 2 (Address = 01h) 7 6 5 4 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 Table 6-5. Interrupt Enable Register 2 Description Bit Field Type Reset Description 3 UCB0TXIE RW 0h USCI_B0 transmit interrupt enable 2 UCB0RXIE RW 0h USCI_B0 receive interrupt enable 1 UCA0TXIE RW 0h USCI_A0 transmit interrupt enable 0 UCA0RXIE RW 0h USCI_A0 receive interrupt enable Figure 6-4. Interrupt Flag Register 1 (Address = 02h) 7 6 5 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Table 6-6. Interrupt Flag Register 1 Description Bit Field Type Reset Description 4 NMIIFG RW 0h Set by the RST/NMI pin 3 RSTIFG RW 0h External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. 2 PORIFG RW 1h Power-On Reset interrupt flag. Set on VCC power-up. 1 OFIFG RW 1h Flag set on oscillator fault. 0 WDTIFG RW 0h Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. |
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