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IP100ALF датащи(PDF) 83 Page - List of Unclassifed Manufacturers

номер детали IP100ALF
подробное описание детали  Integrated 10/100 Ethernet MAC PHY
PDF  97 Pages
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производитель  ETC2 [List of Unclassifed Manufacturers]
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IP100ALF датащи(HTML) 83 Page - List of Unclassifed Manufacturers

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IP100A LF
Preliminary Data Sheet
83/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.15 LatencyTimer
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0d
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
2..0
Reserved
N/A
Reserved for future use.
7..3
LatencyTimer
R/W
Latency Timer. LatencyTimer indicates, in increments of 8 bus
clocks, the length of time which the IP100A LF may hold the PCI
bus in the presence of other bus requestors. Whenever the
IP100A LF asserts the FRAMEN signal, the latency timer is
started. When the latency timer count expires, the IP100A LF
must relinquish the bus as soon as its GNTN signal has been
deasserted.
11.6.16 MaxLat
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3f
Default .......................... 0x0A
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
MaxLat
R
Maximum Latency. MaxLat specifies, in 250 ns increments, how
often the IP100A LF requires bus access while operating as a bus
master. Bits 5 through 1 of the MaxLat value are loaded from the
ConfigParm field within an EEPROM during auto initialization of
the IP100A LF.
11.6.17 MemBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x14
Default .......................... 0x00000000
Width ............................ 32 bits
MemBaseAddress can be disabled via loading of the ConfigParm field from an EEPROM during
auto-ini-tialization of the IP100A LF.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
MemBaseAddrInd
R
Memory Base Address Indicator. When MemBaseAddrInd is a
logic 1, MemBaseAddrInd contains the valid memory base
address.



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