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IP100ALF датащи(PDF) 30 Page - List of Unclassifed Manufacturers

номер детали IP100ALF
подробное описание детали  Integrated 10/100 Ethernet MAC PHY
PDF  97 Pages
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производитель  ETC2 [List of Unclassifed Manufacturers]
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IP100ALF датащи(HTML) 30 Page - List of Unclassifed Manufacturers

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IP100A LF
Preliminary Data Sheet
30/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
3
Auto-Negotiation
Ability
R
1 = Auto-Negotiation capable.
0 = Auto-Negotiation incapable.
If Auto-Negotiation Ability is a logic 1, the IP100A LF is capable of
performing Auto-Negotiation. Auto-Negotiation Ability depends on
the external mode setting of the IP100A LF.
2
Link Status
R
1 = Link is up.
0 = Link is down.
When Link Status is a logic 0, Link Status will remain a logic 0
until the link state changes, and Link Status is read by the host
system.
1
Jabber Detect
R
1 = Jabber detected.
0 = Jabber not detected.
When Jabber Detect is a logic 1, Jabber Detect will remain a logic
0 until the jabber condition no longer exists, and Jabber Detect is
read by the host system.
0
Extended Capability R
1 = Extended capabilities register exists.
11.1.3 PHY Identifier 1
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x02
Default .......................... 0x0243
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
15..0
PHY ID Number
R
Bits 3 through 18 of the OUI.
OUI = 0090C3
11.1.4 PHY Identifier 2
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x03
Default .......................... 0x0D80
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
15..10
PHY ID Number
R
Bits 19 through 24 of the OUI.
9..4
Model Number
R
Manufacturer’s model number.
3..0
Revision Number
R
Four bit manufacturer’s revision number.



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