IP100A LF
Preliminary Data Sheet
24/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
10 Power Management
The IP100A LF supports operating system directed power management according to the ACPI
specification. Power management registers in the PCI configuration space, as defined by the PCI Bus
Power Management Interface specification, Revision 1.0 are described in 10.0.
The IP100A LF supports several power management states. The PowerState field in the PowerMgmtCtrl
register determines IP100A LF’s current power state. The power states are defined as follows:
• D0 Uninitialized (power state 0) is entered as a result of hardware reset, or after a transition from D3
Hot to D0. This state is the same as D0 Active except that the PCI configuration registers are
uninitialized. In this state, the IP100A LF is unable to respond to PCI I/O, memory and configuration
cycles and can not operate as a PCI master The IP100A LF cannot signal wake (PMEN) from the D0
state.
• D0 Active (power state 0) is the normal operational power state for the IP100A LF. In this state, the
PCI configuration registers have been initialized by the system, including the IoSpace,
MemorySpace, and Bus-Master bits in ConfigCommand, so the IP100A LF is able to respond to PCI
I/O, memory and configuration cycles and can operate as a PCI master. The IP100A LF cannot
signal wake (PMEN) from the D0 state.
• D1 (power state 1) is a “light-sleep” state. The IP100A LF optionally supports this state determined
by the D1Support bit in the ConfigParm word in EEPROM. The D1 state allows transition back to D0
with no delay. In this state, the IP100A LF responds to PCI configuration accesses, to allow the
system to change the power state. In D1 the IP100A LF does not respond to any PCI I/O or memory
accesses. The IP100A LF’s function in the D1 state is to recognize wake events and link state events
and pass them on to the system by asserting the PMEN signal on the PCI bus.
• D2 (power state 2) is a partial power-down state. The IP100A LF optionally supports this state
determined by the D2Support bit in the ConfigParm word in EEPROM. D2 allows a faster transition
back to D0 than is possible from the D3 state. In this state, the IP100A LF responds to PCI
configuration accesses, to allow the system to change the power state. In D2 the IP100A LF does
not respond to any PCI I/O or memory accesses. The IP100A LF’s function in the D2 state is to
recognize wake events and link state events and pass them on to the system by asserting the PMEN
signal on the PCI bus.
• D3 Hot (power state 3) is the full power-down state for the IP100A LF. In D3 Hot, the IP100A LF
loses all PCI configuration information except for the value in PowerState. In this state, the IP100A
LF responds to PCI configuration accesses, to allow the system to change the power state back to
D0 Uninitialized. In D3 hot, the IP100A LF does not respond to any PCI I/O or memory accesses.
The IP100A LF’s main responsibility in the D3 Hot state is to recognize wake events and link state
events and signal those to the system by asserting the PMEN signal on the PCI bus.
• D3 Cold (power state undefined) is the power-off state for the IP100A LF. The IP100A LF does not
function in this state. When power is restored, the system guarantees the assertion of hardware
reset, which puts the IP100A LF into the D0 Uninitialized state.
The IP100A LF can generate wake events to the system as a result of Wake Packet reception, Magic
Packet reception, or due to a change in the link status. The WakeEvent register gives the host system
control over which of these events are passed to the system. Wake events are signaled over the PCI bus
using the PMEN pin.
A Wake Packet event is controlled by the WakePktEnable bit in WakeEvent register. WakePktEnable
has no effect when IP100A LF is in the D0 power state, as the wake process can only take place in
states D1, D2, or D3. When the IP100A LF detects a Wake Packet, it signals a wake event on PMEN (if
PMEN assertion is enabled), and sets the WakePktEvent bit in the WakeEvent register. The IP100A LF
can signal that a wake event has occurred when it receives a pre-defined frame from another station.
The host system transfers a set of frame data patterns into the transmit FIFO using the transmit DMA
function before placing the IP100A LF in a power-down state. Once powered down, the IP100A LF
compares receive frames with the frame patterns in the transmit FIFO. When a matching frame is
received (and also passes the filtering mode set in the ReceiveMode register), a wake event is signaled.
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