IP100A LF
Preliminary Data Sheet
53/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
7
EnUpdateStats
R/W
Enable Update Stats Interrupt. Enables the UpdateStats interrupt.
8
EnLinkEvent
R/W
Enable Link Event Interrupt. Enables the LinkEvent interrupt.
9
EnTxDMAComplete R/W
Enable Transmit DMA Complete Interrupt. Enables the
TxDMAComplete interrupt.
10
EnRxDMAComplete R/W
Enable Receive DMA Complete Interrupt. Enables the
RxD-MAComplete interrupt.
11
Reserved
N/A
Reserved for future use.
15..12
Reserved
N/A
Reserved for future use.
11.4.8 IntStatus
Class….......................... LAN I/O Registers, Interrupt
Base Address …............ IoBaseAddress register value
Address Offset …........... 0x4e
Default …....................... 0x0000
Width …......................... 16 bits
IntStatus indicates the source of interrupts and indications on the IP100A LF. All bits except
InterruptStatus are the interrupt causing sources for the IP100A LF. Each interrupt source can be
individually disabled using the IntEnable register. The host system may acknowledge most interrupts by
writing a logic 1 into the corresponding IntStatus bit, which will cause the IP100A LF to clear the interrupt
indication.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
InterruptStatus
R/W
Interrupt Status. InterruptStatus is a logic 1 when the IP100A LF
is driving the bus interrupt signal (INTAN). InterruptStatus is a
logical OR of all the interrupt causing sources after they have
been filtered through the IntEnable register.
1
HostError
R/W
Host Error Interrupt. HostError is a logic 1 when a catastrophic
error related to the bus interface occurs. Catastrophic bus
interface errors include PCI target abort and PCI master abort.
A HostError interrupt requires a setting the GlobalReset and DMA
bits of the AsicCtrl register.
2
TxComplete
R/W
Transmit Complete. TxComplete is a logic 1 when a frame whose
TxIndicate bit in the TFD’s TxFrameControl field is a logic 1, has
been successfully transmitted or for any frame that experiences a
transmission error.
A TxComplete interrupt requires writing to TxStatus register to
advance the status queue.
3
MACControlFrame
R/W
MAC Control Frame Received Interrupt. MACControlFrame is a
logic 1 when a MAC Control frame has been received by the
IP100A LF.
4
RxComplete
R/W
Receive Complete Interrupt. RxComplete is a logic 1 when one or
more entire frames have been received into the receive FIFO.
RxComplete is automatically acknowledged by the receive DMA
logic as it transfers frames.
5
Reserved
R/W
Reserved for future use.
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