IP100A LF
Preliminary Data Sheet
23/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
• LateCollisions: Every occurrence of a late collision (there could be more than one per frame
transmitted) is counted by this statistic.
• FramesAbortedDueToXSColls: If the transmission of a frame had to be aborted due to excessive
collisions, the event is recorded in this statistic.
• CarrierSenseErrors: Frames that were transmitted without error but experienced a loss of carrier are
counted by this statistic.
8.2
Receive Statistics
• FramesReceivedOk: Frames of all types that are received without error are counted here.
• BroadcastFramesReceivedOk: Frames of broadcast destination address that are received without
error are counted here.
• MulticastFramesReceivedOk: Frames of multicast destination address that are received without
error are counted here.
• OctetsReceivedOk: A total octet count for all frames received without error.
• FramesLostRxErrors: This is a count of frames that would otherwise be received by the IP100A LF,
but could not be accepted due to an overrun condition in the RxFifo.
9
PCI Bus Master Operation
The IP100A LF supports all of the PCI memory commands and decides on a burst-by-burst basis which
command to use in order to maximize bus efficiency. The list of PCI memory commands is shown below.
For all commands, “read” and “write” are with respect to the IP100A LF (i.e. read implies the IP100A LF
obtains information from an off-chip location, write implies the IP100A LF sends information to an off-chip
location).
• Memory Read (MR)
• Memory Read Multiple (MRM).
• Memory Write (MW)
• Memory Write Invalidate (MWI)
MR is used for all fetches of descriptor information. For reads of transmit frame data, MR, or MRM is
used, depending upon the remaining number of bytes in the fragment, the amount of free space in the
TxFIFO, and whether the RxDMA Logic is requesting a bus master operation.
MW is used for all descriptor writes. Writes of receive frame data use either MW or MWI, depending
upon the remaining number of bytes in the fragment, the amount of frame data in the RxFIFO, and
whether the TxDMA Logic is requesting a bus master operation.
The IP100A LF provides three configuration bits to control the use of advanced memory commands. The
MWlEnable bit in the ConfigCommand configuration register allows the host to enable or disable the use
of MWI. The MWIDisable bit in DMACtrl allows the host system the ability to disable the use of MWI.
MWIDisable is cleared by default, enabling MWI.
The IP100A LF provides a set of registers that control the PCI burst behavior. These registers allow a
trade-off to be made between PCI bus efficiency and under run/overrun frequency. Arbitration logic
within the PCI Bus Interface block accepts bus requests from the TxDMA Logic and RxDMA Logic. The
TxDMA Logic uses the TxDMABurstThresh register, as described in the TxDMA Logic section, to delay
the bus request until there is enough free space in the TxFIFO for a long, efficient burst. The TxDMA
Logic can also make an urgent bus request as described in the TxDMA Logic section, where burst
efficiency is sacrificed in favor of avoiding a TxFIFO under run condition.
The RxDMA process is described in the RxDMA Logic section. Typically, RxDMA requests will be forwarded
to the Arbiter, however RxDMA Urgent Requests are also possible in order to prevent RxFIFO overruns.
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