IP100A LF
Preliminary Data Sheet
46/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
1
1
1
X
Reserved
In Forced Configuration mode 1, the IP100A LF is configured as
follows:
I/O base address = 0x200
I/O target cycles = enabled
Memory target cycles = disabled
Bus master cycles = enabled
Expansion ROM cycles = disabled.
10
Reserved
N/A
Reserved for future use.
12..11
Reserved
N/A
Reserved for future use.
13
SpeedupMode
R/W
Speed Up Mode. SpeedupMode is used for simulation purposes
only. When SpeedupMode is a logic 1 IP100A LF operation is
modified to decrease simulation time. SpeedupMode can also be
set on reset using signal pin 20.
14
Reserved
N/A
15
Reserved
N/A
Reserved for future use.
16
GlobalReset
W
Global Reset. When GlobalReset is a logic 1, the IP100A LF resets
the logic functions and registers specified by the DMA, FIFO,
Network, Host, and AutoInit bits (related to both the transmit and
receive processes as applicable). The LAN PCI Configuration
Registers are not affected by GlobalReset. GlobalReset is
self-clearing.
17
RxReset
W
Receive Reset. When RxReset is a logic 1 the IP100A LF resets
all of the receive logic functions and registers specified by the
DMA, FIFO, and Network bits. RxReset is self-clearing, and
should not be used after initialization except to recover from
receive errors such as a receive FIFO over run.
18
TxReset
W
Transmit Reset. When TxReset is a logic 1 the IP100A LF resets
all of the transmit logic functions and registers specified by the
DMA, FIFO, and Network bits. TxReset is self clearing, and is
required to be used after a transmit underrun error.
19
DMA
W
DMA Reset. DMA selects (when a logic 1) or excludes (when a
logic 0) the IP100A LF DMA functions and registers (see below)
for/from reset based on the value of the GlobalReset, RxReset,
and TxReset bits. The DMA bit is self-clearing.
20
FIFO
W
FIFO Reset. FIFO selects (when a logic 1) or excludes (when a
logic 0) the IP100A LF FIFO functions and registers for/from reset
based on the value of the GlobalReset, RxReset, and TxReset
bits. The FIFO bit is self-clearing.
21
Network
W
Network Reset. Network selects (when a logic 1) or excludes
(when a logic 0) the IP100A LF network functions and registers
for/from reset based on the value of the GlobalReset, RxReset,
and TxReset bits. The Network bit is self-clearing.
23
AutoInit
W
Automatic Initialization Reset. AutoInit selects (when a logic 1) or
excludes (when a logic 0) the IP100A LF auto-initialization logic
function for/from re-loading IP100A LF parameters from an
EEPROM based on the value of the GlobalReset bit. The AutoInit
bit is self-clearing.
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