IP100A LF
Preliminary Data Sheet
58/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.12 MaxFrameSize
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x5a
Default .......................... 0x1514 or 0x4491 based on the RcvLargeFrames bit in the MACCtrl0 register
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
15..0
MaxFrameSize
R/W
Maximum Frame Size. Received frames with sizes equal to or
larger than MaxFrameSize will be flagged as oversize via the
RxOversizedFrame bit in RxDMAStatus field of the frame’s RFD.
11.4.13 PhyCtrl
Class............................. LAN I/O Registers, External Interface Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5e
Default .......................... 0x00
Width ............................ 8 bits
PhyCtrl contains control bits for the internal MII Management Interface. The MII Management Interface is
used to access registers in the IP100A LF PHY. The host system accesses the MII Management
Interface by writing and reading bit patterns to the PhyCtrl register.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
MgmtClk
R/W
Management Clock. MgmtClk drives the management clock
(MDC) signal to the PHY.
1
MgmtData
R/W
Management Data bit. MgmtData is directly connected to the
MDIO signal connected to the PHY. Data can be written to or read
from the PHY by writing or read MgmtData based on the value of
MgmtDir.
2
MgmtDir
R/W
Management Data Direction. If the MgmtDir is a logic 1, the value
written to MgmtData is driven onto the MDIO signal connected to
the PHY. When MgmtDir is a logic 0, data driven onto MDIO by
the PHY can be read from MgmtData.
3
Reserved
N/A
Reserved for future use.
4
PhyDuplexPolarity
R/W
PHY Duplex Polarity. If PhyDuplexPolarity is a logic 0, the duplex
status signal between the PHY and the MAC is active low.
5
PhyDuplexStatus
R
PHY Duplex Status. If PhyDuplexStatus is a logic 1, the PHY is
operating in full duplex mode. If PhyDuplexStatus is a logic 0, the
PHY is operating in half duplex mode.
6
PhySpeedStatus
R
PHY Speed Status. PhySpeedStatus provides a real-time
indication of the IP100A LF’s PHY speed. If PhySpeedStatus is a
logic 1, the IP100A LF’s PHY is operating at 100Mbps operation.
If PhySpeedStatus is a logic 0, the IP100A LF’s PHY is operating
at 10Mbps operation.
7
PhyLinkStatus
R
PHY Link Status. PhyLinkStatus provides a real-time indication of
the IP100A LF’s PHY link state. If PhyLinkStatus is a logic 1, the
IP100A LF’s PHY link is up. If PhyLinkStatus is a logic 0, the
IP100A LF’s PHY link is down.
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