IP100A LF
Preliminary Data Sheet
56/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
8
FlowControl-
Enable
R/W
Flow Control Enable. If FlowControlEnable is a logic 0, the
IP100A LF treats all incoming frames as data frames. If
FlowControlEnable is a logic 1, flow control is enabled and the
IP100A LF will act upon incoming flow control PAUSE frames. If
FlowControlEnable is a logic 1, FullDuplexEnable should also be
set to a logic 1.
9
RcvFCS
R/W
Receive FCS. If RcvFCS is a logic 1, the IP100A LF will include
the receive frame’s FCS along with the frame data transferred to
the host system. If RcvFCS is a logic 0, the IP100A LF will
remove the FCS from the frame before transferring the frame to
the host system. The state of RcvFCS does not affect the IP100A
LF’s checking of the frame’s FCS and its posting of FCS errors.
RcvFCS should only be changed when the receiver is disabled
(via the RxDisable bit of the MACCtrl1 register) and after resetting
the receive FIFO (via the FIFO bit of the AsicCtrl register).
10
FIFOLoopback
R/W
FIFO Loopback. If FIFOLoopback is a logic 1, the IP100A LF will
enter FIFO Loopback Mode and force data to loopback from the
transmit FIFO directly into the receive FIFO. When using FIFO
Loopback Mode, it is the host system’s responsibility to ensure that
proper interframe spacing is ensured. To accommodate proper
interframe spacing, the host system must not load more than one
transmit frame into the transmit FIFO at a time while in FIFO
Loopback Mode. The TxReset and RxReset bits of the AsicCtrl
register must be set after changing the value of FIFOLoopback.
11
MACLoopback
R/W
MAC Loopback. If MACLoopback is a logic 1, the IP100A LF will
enter MAC Loopback Mode and force data to loopback from the
MAC transmit interface to the MAC receive interface. The
TxReset and RxReset bits in AsicCtrl register must be set after
changing the value of MACLoopback.
15..12
Reserved
N/A
Reserved for future use.
Note: External loopback is controlled by the PHY. To utilize external loopback, the host system must
enable a loopback mode within the PHY using the MII Management Interface. For the true “on-the-wire”
loopback mode, use a loopback plug (connector), clear the FIFOLoopback, and MACLoopback and any
PHY loopback bits to zero, set the FullDuplexEnable bit to a logic 1, and enable the full duplex mode
within the PHY.
11.4.11 MACCtrl1
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x52
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
CollisionDetect
R
Collision Detect. CollisionDetect provides a real-time indication of
the state of the COL signal within the IP100A LF.
1
CarrierSense
R
Carrier Sense. CarrierSense provides a real-time indication of the
state of the CRS signal within IP100A LF.
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