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MPC8280 датащи(PDF) 198 Page - Freescale Semiconductor, Inc

номер детали MPC8280
подробное описание детали  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 датащи(HTML) 198 Page - Freescale Semiconductor, Inc

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System Interface Unit (SIU)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
4-26
Freescale Semiconductor
Table 4-8 describes SIEXR fields.
4.3.2
System Configuration and Protection Registers
The system configuration and protection registers are described in the following sections.
4.3.2.1
Bus Configuration Register (BCR)
The bus configuration register (BCR), shown in Figure 4-21, contains configuration bits for various
features and wait states on the 60x bus.
0
1234
5678
9
10
11
12
13
14
15
Field EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC
10
EDPC
11
EDPC
12
EDPC
13
EDPC
14
EDPC
15
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x10C24
16
17
18
19
20
21
22
23
24
31
Field EDI0
EDI1
EDI2
EDI3
EDI4
EDI5
EDI6
EDI7
—
Reset
0000_0000_0000_0000
R/W
R/W
R
Addr
0x10C26
Figure 4-20. SIU External Interrupt Control Register (SIEXR)
Table 4-8. SIEXR Field Descriptions
Bits
Name
Description
0–15
EDPCx
Edge detect mode for port Cx. The corresponding port C line (PCx) asserts an interrupt request
according to the following:
0 Any change on PCx generates an interrupt request.
1 High-to-low change on PCx generates an interrupt request.
16–23
EDIx
Edge detect mode for IRQ
x. The corresponding IRQ line (IRQx) asserts an interrupt request
according to the following:
0 Low assertion on IRQ
x generates an interrupt request.
1 High-to-low change on IRQ
x generates an interrupt request.



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