MPC8280 datasheet(195/1386 Pages) FREESCALE

195 / 1386 page

System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-23

Figure 4-16 shows the SIMR_H register.

Figure 4-17 shows SIMR_L.

Note the following:

•

SCC/TC/MCC/FCC SIMR bit positions are not affected by their relative priority.

•

The user can clear pending register bits that were set by multiple interrupt events only by clearing

all unmasked events in the corresponding event register.

•

If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt

request to the core, the error vector is issued (if no other interrupts pending). Thus, the user should

always include an error vector routine, even if it contains only an rfi instruction. The error vector

cannot be masked.

Field PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9 PC10 PC11 PC12

PC13

PC14 PC15

Reset

0000_0000_0000_0000

R/W

Addr

0x10C1C

Field

—

IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

—

TMCNT

PIT

PCI

Reset

0000_0000_0000_0000

R/W

Addr

0x10C1E

Figure 4-16. SIMR_H

Field FCC1 FCC2 FCC3

—

MCC11 MCC2

—

SCC1 SCC2 SCC3

SCC4

TC1

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10C20

Field I2C

SPI

RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA

—

TIMER1 TIMER2 TIMER3 TIMER4 —

Reset

0000_0000_0000_0000

R/W

Addr

0x10C22

2 MPC8280 only. Reserved on the other devices.

Figure 4-17. SIMR_L

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