MPC8280 datasheet(199/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-27

Figure 4-9 describes BCR fields.

Field

EBM

APD

L2C

L2D

PLDP DREF

DAM

EAV ETM LETM EPAR LEPAR

Reset note 1

000_0000_0000_0000

R/W

Field

NPQM

—

EXDD LPLDP

—

SPAR ISPS

—

Reset

0000_0000_000

note 1

0000

R/W

Addr

0x10024

1 Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.”

Figure 4-21. Bus Configuration Register (BCR)

Table 4-9. BCR Field Descriptions

Bits

Name

Description

EBM

External bus mode.

0 Single MPC8280 bus mode is assumed

1 60x-compatible bus mode. For more information refer to Section 8.2, “Bus Configuration.”

1–3

APD

Address phase delay. Specifies the number of address tenure wait states for address operations

initiated by a 60x bus master. BCR[APD] specifies the number of address tenure wait states for

address operations initiated by 60x-bus devices. APD indicates how many cycles the MPC8280

should wait for ARTRY, but because it is assumed that ARTRY can be asserted (by other masters)

only on cachable address spaces, APD is considered only on transactions that hit one of the

60x-assigned memory controller banks and have the GBL signal asserted during address phase.

L2C

Secondary cache controller. See Chapter 12, “Secondary (L2) Cache Support.”

0 No secondary cache controller is assumed.

1 An external secondary cache controller is assumed.

5–7

L2D

L2 cache hit delay. Controls the number of clock cycles from the assertion of TS until HIT is valid.

PLDP

Pipeline maximum depth. See Section 8.4.5, “Pipeline Control.”

0 The pipeline maximum depth is one.

1 The pipeline maximum depth is zero.

DREF

Disable reflection. Disables reflection of system bus reflection on external pins of internal transfers

on 60x bus.

0 Enable reflection

1 Disable reflection

DAM

Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM). This bit is similar to

BCR[EXDD] but with opposite polarity.

0 The memory controller inserts one wait state between the assertion of TS and the assertion of CS

when external master accesses an address space controlled by the memory controller.

1 The memory controller asserts CS on the cycle following the assertion of TS by external master

accessing an address space controlled by the memory controller.

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