MPC8280 datasheet(50/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

4-18

SIU Interrupt Vector Register (SIVEC) ................................................................................ 4-24

4-19

Interrupt Table Handling Example........................................................................................ 4-25

4-20

SIU External Interrupt Control Register (SIEXR) ................................................................ 4-26

4-21

Bus Configuration Register (BCR) ....................................................................................... 4-27

4-22

PPC_ACR ............................................................................................................................. 4-29

4-23

PPC_ALRH........................................................................................................................... 4-30

4-24

PPC_ALRL ........................................................................................................................... 4-31

4-25

LCL_ACR ............................................................................................................................. 4-31

4-26

LCL_ALRH .......................................................................................................................... 4-32

4-27

LCL_ALRL........................................................................................................................... 4-33

4-28

SIU Model Configuration Register (SIUMCR) .................................................................... 4-33

4-29

Internal Memory Map Register (IMMR) .............................................................................. 4-36

4-30

System Protection Control Register (SYPCR)...................................................................... 4-37

4-31

60x Bus Transfer Error Status and Control Register 1 (TESCR1) ....................................... 4-39

4-32

60x Bus Transfer Error Status and Control Register 2 (TESCR2) ....................................... 4-41

4-33

Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) ................................ 4-42

4-34

Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) ................................ 4-43

4-35

Time Counter Status and Control Register (TMCNTSC) ..................................................... 4-44

4-36

Time Counter Register (TCMCNT)...................................................................................... 4-45

4-37

Time Counter Alarm Register (TMCNTAL) ........................................................................ 4-45

4-38

Periodic Interrupt Status and Control Register (PISCR)....................................................... 4-46

4-39

Periodic interrupt Timer Count Register (PITC) .................................................................. 4-47

4-40

Periodic Interrupt Timer Register (PITR) ............................................................................. 4-48

4-41

PCI Base Registers (PCIBRx)............................................................................................... 4-49

4-42

PCI Mask Register (PCIMSKx)............................................................................................ 4-50

5-1

Power-on Reset Flow .............................................................................................................. 5-3

5-2

Reset Status Register (RSR).................................................................................................... 5-4

5-3

Reset Mode Register (RMR)................................................................................................... 5-5

5-4

Hard Reset Configuration Word.............................................................................................. 5-8

5-5

Single Chip with Default Configuration ............................................................................... 5-10

5-6

Configuring a Single Chip from EPROM............................................................................. 5-11

5-7

Configuring Multiple Chips .................................................................................................. 5-12

6-1

MPC8280 External Signals .....................................................................................................6-2

7-1

Signal Groupings..................................................................................................................... 7-2

8-1

Single-MPC8280 Bus Mode ................................................................................................... 8-3

8-2

60x-Compatible Bus Mode ..................................................................................................... 8-4

8-3

Basic Transfer Protocol........................................................................................................... 8-5

8-4

Address Bus Arbitration with External Bus Master................................................................ 8-8

8-5

Address Pipelining .................................................................................................................. 8-9

8-6

Interface to Different Port Size Devices ............................................................................... 8-16

8-7

Retry Cycle ........................................................................................................................... 8-22

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