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MPC8280 датащи(PDF) 202 Page - Freescale Semiconductor, Inc |
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MPC8280 датащи(HTML) 202 Page - Freescale Semiconductor, Inc |
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202 / 1386 page ![]() System Interface Unit (SIU) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 4-30 Freescale Semiconductor Table 4-10 describes PPC_ACR fields. 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) The 60x bus arbitration-level registers, shown in Figure 4-23 and Figure 4-24, define arbitration priority of MPC8280 bus masters. Priority field 0 has highest-priority. For information about MPC8280 bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10. Table 4-10. PPC_ACR Field Descriptions Bits Name Description 0–1 — Reserved, should be cleared. 2 DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for 60x bus master-initiated data operations. This is the minimum delay between TS and DBG. 0DBG is asserted with TS if the data bus is free. 1DBG is asserted one cycle after TS if the data bus is not busy. See Section 8.5.1, “Data Bus Arbitration.” 3 EARB External arbitration. 0 Internal arbitration is performed. See Section 8.3.1, “Arbitration Phase.” 1 External arbitration is assumed. 4–7 PRKM Parking master. 0000 CPM high request level refers to the IDMA which involves peripherals and the following serial channels (SCC, SPI, SMC, and I2C) 0001 CPM middle request level refers to all other serial channels (FCCs and MCCs) 0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See Section 30.7.1, “FCC Function Code Registers (FCRx).”) 0011 PCI request level. Reserved on all other devices. 0100 Reserved 0101 Reserved 0110 Internal core 0111 External master 1 1000 External master 2 1001 External master 3 Values 1010–1111 are reserved. 03 47 8 11 12 15 Field Priority Field 0 Priority Field 1 Priority Field 2 Priority Field 3 Reset 0000 0001 0010 0110 R/W R/W Addr 0x1002C 16 19 20 23 24 27 28 31 Field Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7 Reset 0011 0100 0101 0111 R/W R/W Addr 0x1002E Figure 4-23. PPC_ALRH |
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