MPC8280 datasheet(27/1386 Pages) FREESCALE

27 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xxvii

Contents

Paragraph

Number

Title

Page

Number

22.13

SCC HDLC Programming Examples .......................................................................... 22-16

22.13.1

SCC HDLC Programming Example #1................................................................... 22-16

22.13.2

SCC HDLC Programming Example #2................................................................... 22-18

22.14

HDLC Bus Mode with Collision Detection................................................................. 22-18

22.14.1

HDLC Bus Features................................................................................................. 22-20

22.14.2

Accessing the HDLC Bus ........................................................................................ 22-20

22.14.3

Increasing Performance ........................................................................................... 22-21

22.14.4

Delayed RTS Mode.................................................................................................. 22-22

22.14.5

Using the Time-Slot Assigner (TSA) ...................................................................... 22-23

22.14.6

HDLC Bus Protocol Programming.......................................................................... 22-23

22.14.6.1

Programming GSMR and PSMR for the HDLC Bus Protocol ........................... 22-23

22.14.6.2

HDLC Bus Controller Programming Example.................................................... 22-24

Chapter 23

SCC BISYNC Mode

23.1

Features .......................................................................................................................... 23-2

23.2

SCC BISYNC Channel Frame Transmission ................................................................ 23-2

23.3

SCC BISYNC Channel Frame Reception ..................................................................... 23-3

23.4

SCC BISYNC Parameter RAM ..................................................................................... 23-3

23.5

SCC BISYNC Commands ............................................................................................. 23-4

23.6

SCC BISYNC Control Character Recognition .............................................................. 23-5

23.7

BISYNC SYNC Register (BSYNC).............................................................................. 23-7

23.8

SCC BISYNC DLE Register (BDLE) ........................................................................... 23-8

23.9

Sending and Receiving the Synchronization Sequence ................................................. 23-9

23.10

Handling Errors in the SCC BISYNC ........................................................................... 23-9

23.11

BISYNC Mode Register (PSMR)................................................................................ 23-10

23.12

SCC BISYNC Receive BD (RxBD) ............................................................................ 23-12

23.13

SCC BISYNC Transmit BD (TxBD)........................................................................... 23-14

23.14

BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).......................... 23-15

23.15

SCC Status Registers (SCCS)...................................................................................... 23-16

23.16

Programming the SCC BISYNC Controller ................................................................ 23-17

23.17

SCC BISYNC Programming Example ........................................................................ 23-18

Chapter 24

SCC Transparent Mode

24.1

Features .......................................................................................................................... 24-1

24.2

SCC Transparent Channel Frame Transmission Process............................................... 24-2

24.3

SCC Transparent Channel Frame Reception Process .................................................... 24-2

24.4

Achieving Synchronization in Transparent Mode ......................................................... 24-3

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