MPC8280 datasheet(35/1386 Pages) FREESCALE

35 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xxxv

Contents

Paragraph

Number

Title

Page

Number

31.3.5.4

Peak and Minimum Cell Rate Traffic Type (UBR+)........................................... 31-13

31.3.6

Determining the Priority of an ATM Channel ......................................................... 31-13

31.4

VCI/VPI Address Lookup Mechanism........................................................................ 31-13

31.4.1

External CAM Lookup ............................................................................................ 31-14

31.4.2

Address Compression .............................................................................................. 31-15

31.4.2.1

VP-Level Address Compression Table (VPLT) .................................................. 31-16

31.4.2.2

VC-Level Address Compression Tables (VCLTs)............................................... 31-17

31.4.3

Misinserted Cells ..................................................................................................... 31-18

31.4.4

Receive Raw Cell Queue ......................................................................................... 31-18

31.5

Available Bit Rate (ABR) Flow Control...................................................................... 31-19

31.5.1

The ABR Model....................................................................................................... 31-20

31.5.1.1

ABR Flow Control Source End-System Behavior .............................................. 31-20

31.5.1.2

ABR Flow Control Destination End-System Behavior ....................................... 31-21

31.5.1.3

ABR Flowcharts .................................................................................................. 31-21

31.5.2

RM Cell Structure .................................................................................................... 31-26

31.5.2.1

RM Cell Rate Representation .............................................................................. 31-26

31.5.3

ABR Flow Control Setup......................................................................................... 31-27

31.6

OAM Support .............................................................................................................. 31-27

31.6.1

ATM-Layer OAM Definitions ................................................................................. 31-27

31.6.2

Virtual Path (F4) Flow Mechanism ......................................................................... 31-28

31.6.3

Virtual Channel (F5) Flow Mechanism ................................................................... 31-28

31.6.4

Receiving OAM F4 or F5 Cells ............................................................................... 31-28

31.6.5

Transmitting OAM F4 or F5 Cells........................................................................... 31-28

31.6.6

Performance Monitoring.......................................................................................... 31-29

31.6.6.1

Running a Performance Block Test ..................................................................... 31-30

31.6.6.2

PM Block Monitoring.......................................................................................... 31-30

31.6.6.3

PM Block Generation .......................................................................................... 31-31

31.6.6.4

BRC Performance Calculations ........................................................................... 31-32

31.7

User-Defined Cells (UDC) .......................................................................................... 31-32

31.7.1

UDC Extended Address Mode (UEAD).................................................................. 31-32

31.8

ATM Layer Statistics ................................................................................................... 31-33

31.9

ATM-to-TDM Interworking ........................................................................................ 31-33

31.9.1

Automatic Data Forwarding .................................................................................... 31-33

31.9.2

Using Interrupts in Automatic Data Forwarding ..................................................... 31-34

31.9.3

Timing Issues ........................................................................................................... 31-35

31.9.4

Clock Synchronization (SRTS and Adaptive FIFOs) .............................................. 31-35

31.9.5

Mapping TDM Time Slots to VCs........................................................................... 31-35

31.9.6

CAS Support ............................................................................................................ 31-35

31.9.7

Trunk Condition....................................................................................................... 31-36

31.9.8

ATM-to-ATM Data Forwarding............................................................................... 31-36

31.10

ATM Memory Structure............................................................................................... 31-36

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