MPC8280 datasheet(194/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-22

Freescale Semiconductor

Figure 4-15 shows SIPNR_L fields.

When a pending interrupt is handled, the user clears the corresponding SIPNR bit. However, if an event

cleared.

SIPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing

zeros to this register has no effect.

Note that the SCC/FCC/MCC SIPNR bit positions are not changed according to their relative priority.

4.3.1.5

SIU Interrupt Mask Registers (SIMR_H and SIMR_L)

Each bit in the SIU interrupt mask register (SIMR) corresponds to a interrupt source. The user masks an

interrupt by clearing and enables an interrupt by setting the corresponding SIMR bit. When a masked

interrupt occurs, the corresponding SIPNR bit is set, regardless of the SIMR bit although no interrupt

request is passed to the core.

If an interrupt source requests interrupt service when the user clears its SIMR bit, the request stops. If the

user sets the SIMR bit later, a previously pending interrupt request is processed by the core, according to

its assigned priority. The SIMR can be read by the user at any time.

111213

Field FCC1 FCC2 FCC3

—

MCC12 MCC2

—

SCC1 SCC2 SCC3 SCC4

TC2

—

Reset

0000_0000_0000_00001

R/W

Addr

0x10C0C

Field I2C

SPI

RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA

—

TIMER1 TIMER2 TIMER3 TIMER4 —

Reset

0000_0000_0000_0001

R/W

Addr

0x10C0E

1 These fields are zero after reset because their corresponding mask register bits are cleared (disabled).

2 MPC8280 only. Reserved on all other devices.

Figure 4-15. SIPNR_L

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