MPC8280 datasheet(54/1386 Pages) FREESCALE

54 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

liv

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

11-21

ACTTORW = 2 (2 Clock Cycles)....................................................................................... 11-40

11-22

CL = 2 (2 Clock Cycles) ..................................................................................................... 11-40

11-23

LDOTOPRE = 2 (–2 Clock Cycles).................................................................................... 11-41

11-24

WRC = 2 (2 Clock Cycles) ................................................................................................. 11-41

11-25

RFRC = 4 (6 Clock Cycles) ................................................................................................ 11-42

11-26

EAMUX = 1........................................................................................................................ 11-42

11-27

BUFCMD = 1...................................................................................................................... 11-43

11-28

SDRAM Single-Beat Read, Page Closed, CL = 3 .............................................................. 11-43

11-29

SDRAM Single-Beat Read, Page Hit, CL = 3 .................................................................... 11-44

11-30

SDRAM Two-Beat Burst Read, Page Closed, CL = 3........................................................ 11-44

11-31

SDRAM Four-Beat Burst Read, Page Miss, CL = 3........................................................... 11-44

11-32

SDRAM Single-Beat Write, Page Hit................................................................................. 11-45

11-33

SDRAM Three-Beat Burst Write, Page Closed .................................................................. 11-45

11-34

SDRAM Read-after-Read Pipeline, Page Hit, CL = 3........................................................ 11-45

11-35

SDRAM Write-after-Write Pipelined, Page Hit.................................................................. 11-46

11-36

SDRAM Read-after-Write Pipelined, Page Hit .................................................................. 11-46

11-37

SDRAM Mode-Set Command Timing ............................................................................... 11-47

11-38

Mode Data Bit Settings ....................................................................................................... 11-47

11-39

SDRAM Bank-Staggered CBR Refresh Timing................................................................. 11-48

11-40

GPCM-to-SRAM Configuration......................................................................................... 11-52

11-41

GPCM Peripheral Device Interface .................................................................................... 11-54

11-42

GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................................. 11-55

11-43

GPCM Memory Device Interface ....................................................................................... 11-55

11-44

GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)....................... 11-56

11-45

GPCM Memory Device Basic Timing (ACS

≠ 00, CSNT = 1, TRLX = 0)....................... 11-56

11-46

GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) .................... 11-57

11-47

GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1) .................... 11-57

11-48

GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) ................... 11-58

11-49

GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) ................... 11-58

11-50

GPCM Read Followed by Read (ORx[29–30] = 00, Fastest Timing) ................................ 11-59

11-51

GPCM Read Followed by Read (ORx[29–30] = 01).......................................................... 11-60

11-52

GPCM Read Followed by Write (ORx[29–30] = 01) ......................................................... 11-60

11-53

GPCM Read Followed by Write (ORx[29–30] = 10) ......................................................... 11-61

11-54

External Termination of GPCM Access.............................................................................. 11-62

11-55

User-Programmable Machine Block Diagram.................................................................... 11-64

11-56

RAM Array Indexing .......................................................................................................... 11-65

11-57

Memory Refresh Timer Request Block Diagram ............................................................... 11-66

11-58

Memory Controller UPM Clock Scheme for Integer Clock Ratios.................................... 11-68

11-59

Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)

Clock Ratios ................................................................................................................... 11-69

11-60

UPM Signals Timing Example ........................................................................................... 11-70

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