MPC8280 datasheet(62/1386 Pages) FREESCALE

62 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxii

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

31-38

ATM Pace Control Data Structure ...................................................................................... 31-62

31-39

The APC Scheduling Table Structure ................................................................................. 31-63

31-40

Control Slot ......................................................................................................................... 31-64

31-41

Transmit Buffers and BD Table Example ........................................................................... 31-65

31-42

Receive Static Buffer Allocation Example ......................................................................... 31-66

31-43

Receive Global Buffer Allocation Example ....................................................................... 31-67

31-44

Free Buffer Pool Structure .................................................................................................. 31-67

31-45

Free Buffer Pool Entry ........................................................................................................ 31-68

31-46

AAL5 RxBD ....................................................................................................................... 31-69

31-47

AAL1 RxBD ....................................................................................................................... 31-71

31-48

AAL0 RxBD ....................................................................................................................... 31-72

31-49

User-Defined Cell—RxBD Extension ................................................................................ 31-73

31-50

AAL5 TxBD ....................................................................................................................... 31-74

31-51

AAL1 TxBD ....................................................................................................................... 31-75

31-52

AAL0 TxBDs ...................................................................................................................... 31-76

31-53

User-Defined Cell—TxBD Extension ................................................................................ 31-77

31-54

AAL1 Sequence Number (SN) Protection Table ................................................................ 31-78

31-55

Interrupt Queue Structure.................................................................................................... 31-79

31-56

Interrupt Queue Entry ......................................................................................................... 31-80

31-57

UTOPIA Master Mode Signals ........................................................................................... 31-81

31-58

UTOPIA Slave Mode Signals ............................................................................................. 31-83

31-59

FCC ATM Mode Register (FPSMR) .................................................................................. 31-86

31-60

ATM Event Register (FCCE)/FCC Mask Register (FCCM) .............................................. 31-88

31-61

COMM_INFO Field ........................................................................................................... 31-89

31-62

FCC Transmit Internal Rate Register (FTIRR)................................................................... 31-92

31-63

FCC Transmit Internal Rate Clocking ................................................................................ 31-92

31-64

FCC Transmit Internal Rate Port Enable Register (FIRPERx)........................................... 31-94

31-65

FCC Internal Rate Event Register (FIRERx)...................................................................... 31-95

31-66

FCC Internal Rate Selection Register HI (FIRSRx_HI) ..................................................... 31-96

31-67

FCC Internal Rate Selection Register LO (FIRSRx_LO)................................................... 31-96

31-68

AAL1 CES SRTS Generation Using External Logic.......................................................... 31-97

31-69

AAL1 CES SRTS Clock Recovery Using External Logic ................................................. 31-98

32-1

AAL1 Transmit Cell Format ................................................................................................. 32-3

32-2

AAL1 SDT Cell Types.......................................................................................................... 32-3

32-3

AAL1 Framing Formats........................................................................................................ 32-4

32-4

AAL1 CES Receiver Data flow ............................................................................................ 32-6

32-5

ATM-to-TDM Interworking.................................................................................................. 32-7

32-6

TDM-to-ATM Interworking.................................................................................................. 32-8

32-7

Mapping CAS Data on a Serial Interface............................................................................ 32-10

32-8

Internal CAS Block Formats............................................................................................... 32-11

32-9

Mapping CAS Entry............................................................................................................ 32-12

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