MPC8280 datasheet(201/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-29

4.3.2.2

60x Bus Arbiter Configuration Register (PPC_ACR)

The 60x bus arbiter configuration register (PPC_ACR), shown in Figure 4-22, defines the arbiter modes

and parked master on the 60x bus.

EXDD

External master delay disable. Generally, the MPC8280 adds one clock cycle delay for each external

master access to a region controlled by the memory controller. This occurs because the external

master drives the address on the external pins (compared to internal master, like the MPC8280’s

DMA, which drives the address on an internal bus in the chip). Thus, it is assumed that an additional

cycle is needed for the memory controllers banks to complete the address match. However in some

cases (when the bus is operated in low frequency), this extra cycle is not needed. The user can

disable the extra cycle by setting EXDD.

0 The memory controller inserts one wait state between the assertion of TS and the assertion of CS

when external master accesses an address space controlled by the memory controller.

1 The memory controller asserts CS on the cycle following the assertion of TS by external master

accessing an address space controlled by the memory controller.

LPLDP Local bus pipeline maximum depth. See Section 8.4.5, “Pipeline Control.”

0 The local bus pipeline maximum depth is one.

1 The local bus pipeline maximum depth is zero.

23–25

—

Reserved, should be cleared.

SPAR

Slave parity check. If set enables parity check on 60x bus transactions to the MPC8280's internal

memory space. In case of a parity error a core machine check is asserted and the error is reported

in TESCR1[ISBE,PAR] and TESCR2[REGS,DPR,PCI0,PCI1,LCL].

ISPS

Internal space port size. Defines the port size of MPC8280’s internal space region as seen to external

masters. Setting ISPS enables a 32-bit master to access MPC8280 internal space.

0 MPC8280 acts as a 64-bit slave to external masters accesses to its internal space.

1 MPC8280 acts as a 32-bit slave to external masters accesses to its internal space.

28–31

—

Reserved, should be cleared.

123

Field

—

DBGD

EARB1

PRKM

Reset

000

See note

0010

R/W

Addr

0x10028

1 Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.”

Figure 4-22. PPC_ACR

Table 4-9. BCR Field Descriptions (continued)

Bits

Name

Description

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