MPC8280 datasheet(200/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-28

Freescale Semiconductor

EAV

Enable address visibility. Normally, when the MPC8280 is in single-MPC8280 bus mode, the bank

select signals for SDRAM accesses are multiplexed on the 60x bus address lines. So, for SDRAM

accesses, the internal address is not visible for debug purposes. However the bank select signals

can also be driven on dedicated pins (see SIUMCR[APPC]). In this case EAV can be used to force

address visibility.

0 Bank select signals are driven on 60x bus address lines. There is no full address visibility.

1 Bank select signals are not driven on address bus. During READ and WRITE commands to

SDRAM devices, the full address is driven on 60x bus address lines.

ETM

Compatibility mode enable. See Section 8.4.3.8, “Extended Transfer Mode.”

0 Strict 60x bus mode. Extended transfer mode is disabled.

1 Extended transfer mode is enabled.

LETM

Local bus compatibility mode enable. See Section 8.4.3.8, “Extended Transfer Mode.”

0 Extended transfer mode is disabled on the local bus.

1 Extended transfer mode is enable on the local bus.

Note that if the local bus memory controller is configured to work with read-modify-write parity, LETM

must be cleared.

EPAR

Even parity. Determines odd or even parity on the 60x bus.

0 Odd parity

1Even parity

Writing the memory with EPAR = 1 and reading the memory with EPAR = 0 generates parity errors

for testing.

LEPAR Local bus even parity. Determines odd or even parity on the local bus.

0 Odd parity

1Even parity

Writing the memory with LEPAR = 1 and reading the memory with LEPAR = 0 generates parity errors

for testing.

16–18

NPQM Non MPC8280 master. Identifies the type of bus masters which are connected to the arbitration lines

when the MPC8280 is in internal arbiter mode. Possible types are MPC8280 master and

non-MPC8280 master. This field is related to the data pipelining bits (BRx[DR]) in the memory

controller. Because an external bus master that is not a MPC8280 cannot use the data pipelining

feature, the MPC8280, which controls the memory, needs to know when a non-MPC8280 master is

accessing the memory and handle the transaction differently.

NPQM[0] designates the type of master connected to the set of pins BR, BG, and DBG.

NPQM[1] designates the type of master connected to the set of pins EXT_BR2, EXT_BG2, and

EXT_DBG2.

NPQM[2] designates the type of master which is connected to the set of pins EXT_BR3, EXT_BG3

and EXT_DBG3

0 The bus master connected to the arbitration lines is a MPC8280.

1 The bus master connected to the arbitration lines is not a MPC8280.

19–20

—

Reserved, should be cleared.

Table 4-9. BCR Field Descriptions (continued)

Bits

Name

Description

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